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Preliminary Technical Data
FEATURES
3 V to 5 V supply operation True 12-bit accuracy 5 V operation @ <10 A Fast 3-wire serial input Fast 1 s settling time 2.4 MHz, 4-quadrant multiply BW Upgrade for DAC8043 and DAC8043A Standard and rotated pinout
12-Bit Serial Input Multiplying DAC AD5441
FUNCTIONAL BLOCK DIAGRAM
VDD VREF
AD5441
RFB DAC 12 IOUT
LD
DAC REG 12
06492-001
CLK SRI
12-BIT SHIFT REGISTER
GND
APPLICATIONS
Ideal for PLC applications in industrial control Programmable amplifiers and attenuators Digitally controlled calibration and filters Motion control systems
Figure 1.
GENERAL DESCRIPTION
The AD5441 is an improved high accuracy 12-bit multiplying digital-to-analog converter (DAC) in space-saving 8-lead packages. Featuring serial input, double buffering, and excellent analog performance, the AD5441 is ideal for applications where PC board space is at a premium. Improved linearity and gain error performance permit reduced part counts through the elimination of trimming components. Separate input clock and load DAC control lines allow full user control of data loading and analog output. The circuit consists of a 12-bit serial-in/parallel-out shift register, a 12-bit DAC register, a 12-bit CMOS DAC, and control logic. Serial data is clocked into the input register on the rising edge of the CLOCK pulse. When the new data-word is clocked in, it is loaded into the DAC register with the LD input pin. Data in the DAC register is converted to an output current by the DAC. Consuming only 10 A from a single 5 V power supply, the AD5441 is the ideal low power, small size, high performance solution to many application problems. The AD5441 is specified over the extended industrial (-40C to +125C) temperature range. It is available in an 8-lead LFCSP and an 8-lead MSOP.
0.5 TA = -40C, +25C, +85C 0.4 VDD = +5V VREF = -10V 0.3 0.2
INL (LSB)
0.1 0 -0.1 -0.2 -0.3 -0.4 0 512 1024 1536 2048 CODE 2560 3072 3584 4096
06492-002
-0.5
Figure 2. Integral Nonlinearity Error vs. Code
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
AD5441 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Table of Contents .............................................................................. 2 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics............................................................. 3 Absolute Maximum Ratings............................................................ 4 ESD Caution.................................................................................. 4 Pin Configurations and Function Descriptions ........................... 5
Preliminary Technical Data
Typical Performance Characteristics ..............................................7 Terminology .................................................................................... 10 Parameter Definitions.................................................................... 11 General Circuit Information..................................................... 11 Output Impedance ..................................................................... 11 Applications Information.......................................................... 11 Unipolar 2-Quadrant Multiplying ........................................... 11 Bipolar 4-Quadrant Multiplying .............................................. 12 Interface Logic Information...................................................... 12 Digital Section ............................................................................ 12 Outline Dimensions ....................................................................... 13
REVISION HISTORY
3/07--Revision PrA: Preliminary Version
Rev. PrA | Page 2 of 16
Preliminary Technical Data SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
@ VDD = 5 V, VREF = 10 V, -40C < TA < +125C, unless otherwise noted. Table 1.
Parameter STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Gain Temperature Coefficient1 Output Leakage Current Zero-Scale Error REFERENCE INPUT Input Resistance Input Capacitance1 ANALOG OUTPUT Output Capacitance1 DIGITAL INPUTS Digital Input Low Digital Input High Input Leakage Current Input Capacitance1 INTERFACE TIMING1, 2 Data Setup Data Hold Clock Width High Clock Width Low Load Pulse Width LD DAC High to MSB CLK High LSB CLK to LD DAC AC CHARACTERISTICS1 Output Current Settling Time DAC Glitch Digital Feedthrough Feedthrough (VOUT/VREF) Total Harmonic Distortion Output Noise Density Multiplying Bandwidth Power Supply Range Positive Supply Current Power Dissipation Power Supply Sensitivity
1 2
AD5441
Symbol N INL DNL GFSE TCGFS ILKG IZSE
Min
Typ
Max 12 1.0 1.0 2.0 5 5 25 0.03 0.15
Unit Bits LSB LSB LSB ppm/C nA nA LSB LSB k pF pF pF
Condition
All grades monotonic to 12 bits Data = FFFH IOUT pin measured Data = 000H, IOUT pin measured TA = -40C, +125C, Data = 000H, IOUT pin measured Data = 000H TA = -40C, +125C, Data = 000H Absolute temperature coefficient < 50 ppm/C
RREF CREF COUT
7 5 25 30
15
Data = 000H Data = FFFH
VIL VIH IIL CIL tDS tDH tCH tCL tLD tLD1 tASB tS Q FT THD en BW VDD RANGE IDD PDISS PSS
0.8 2.4 1 10 10 5 25 25 25 0 0 1 20 TBD 1 -85 17 2.4 3 5 10 50 0.002
V V A pF ns ns ns ns ns ns ns s nVs mV p-p dB nV/Hz MHz V A W %/%
VLOGIC = 0 V to 5 V VLOGIC = 0 V
To 0.01% of full-scale, external op amp OP42 Data = 000H to FFFH to 000H, VREF = 0 V VREF = 20 V p-p, data = 000H, f = 10 kHz VREF = 6 V rms, data = FFFH, f = 1 kHz 10 Hz to 100 kHz between RFB and IOUT -3 dB, VOUT/VREF, VREF = 100 mV rms, data = FFFH VLOGIC = 0 V or VDD VLOGIC = 0 V or VDD VDD = 5%
These parameters are guaranteed by design and not subject to production testing. All input control signals are specified with tR = tF = 2 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
Rev. PrA | Page 3 of 16
AD5441 ABSOLUTE MAXIMUM RATINGS
The AD5441 contains 346 transistors. The die size measures 70.3 mm x 57.1 mm = 4014 square mm. Table 2.
Parameter VDD to GND VREF to GND RFB to GND Logic Inputs to GND VIOUT to GND IOUT Short Circuit to GND Package Power Dissipation Thermal Resistance JA: 8-Lead MSOP JA: 8-Lead LFCSP1 JC: 8-Lead MSOP JC: 8-Lead LFCSP1 Maximum Junction Temperature (TJ max) Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 sec)
1
Preliminary Technical Data
Rating -0.3 V, +8 V 18 V 18 V -0.3 V, VDD + 0.3 V -0.3 V, VDD + 0.3 V 50 mA (TJ max - TA)/JA 142C/W 75C/W 44C/W 18C/W 150C -40C to +125C -65C to +150C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Exposed pad soldered to application board.
Rev. PrA | Page 4 of 16
Preliminary Technical Data PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VREF RFB IOUT GND 1 2 3 4 AD5441 TOP VIEW
(Not to Scale)
AD5441
8 VDD 7 CLK 5 SRI 5 LD
VREF 1 RFB 2 IOUT 3
8
VDD CLK
AD5441
7 6
SRI TOP VIEW GND 4 (Not to Scale) 5 LD
Figure 3. 8-LeadLFCSP Pin Configuration
Figure 4. 8-Lead MSOP Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 Mnemonic VREF RFB IOUT GND LD SRI CLK VDD Descriptions DAC Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code. Internal Matching Feedback Resistor. Connect to external op amp output. DAC Current Output, full-scale output 1 LSB less than reference input voltage -VREF. Analog and Digital Ground. Load Strobe, Level-Sensitive Digital Input. Transfers shift-register data to DAC register while active low. See Table 4 for operation. 12-Bit Serial Register Input, data loads directly into the shift register MSB first. Extra leading bits are ignored. Clock Input, positive-edge clocks data into shift register. Positive Power Supply Input. Specified range of operation 5 V 10%.
Rev. PrA | Page 5 of 16
AD5441
SRI D11 D10 D9 D8 D7 D6 D5 D4 D3 D2
Preliminary Technical Data
D1 D0
CLK
tLD1
LD DATA LOADED MSB(D11) FIRST Dxx DAC REGISTER LOAD
tASB
SRI
tDS
CLK
tDH tCH tLD tS
tCL
LD
FS VOUT ZS
Figure 5. Timing Diagram
Table 4. Control-Logic Truth Table
CLK LD H L Serial Shift Register Function Shift-register-data advanced one bit
1
DAC Register Function Latched Updated with current shift register contents Latched all 12 bits
1 H or L L
1
No effect No effect
equals positive logic transition.
Rev. PrA | Page 6 of 16
06492-005
1LSB ERROR BAND
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
35 30 25 SS = 200 UNITS TA = 25C VDD = 5V VREF = 10V 10 VDD = 5V VLOGIC = 0V OR VDD 1
AD5441
FREQUENCY
IDD (A)
20 15 10 5
0.1
0.01
0.5 -0.5 0 TOTAL UNADJUSTED ERROR (LSB)
1.0
-35
-15
5 25 45 65 TEMPERATURE (C)
85
105
125
Figure 6. Total Unadjusted Error Histogram
3500 50 SS = 200 UNITS TA = -40C TO +85C VDD = 5V VREF = 10V 3000 2500
Figure 9. Supply Current IDD vs. Temperature
VDD = 5V VREF = 10V TA = 25C
40
CODE = 0xF55
FREQUENCY
30
IDD (A)
2000 1500 CODE = 0x800 1000 CODE = 0xFFF
20
10
500
06492-010 06492-011
0
0
1 FULL SCALE TEMPCO (ppm/C)
2
06492-007
0 1k
10k
100k 1M FREQUENCY (Hz)
10M
100M
Figure 7. Full-Scale Output Temperature Coefficient Histogram
100
0.5 TA = 25C VDD = 5V
Figure 10. Supply Current IDD vs. Clock Frequency
VDD = 5V 10%
SUPPLY CURRENT I DD (mA)
0.4
80
0.3
PSRR (dB)
60
0.2
40
0.1
0
0.5
1.0
1.5 2.0 2.5 3.0 3.5 LOGIC INPUT VOLTAGE (V)
4.0
4.5
5.0
06492-008
0
20 1k
10k
100k FREQUENCY (Hz)
1M
10M
Figure 11. Power Supply Rejection Ratio (PSRR) vs. Frequency Figure 8. Supply Current IDD vs. Logic Input Voltage
Rev. PrA | Page 7 of 16
06492-009
06492-006
0 -1.0
0.001 -55
AD5441
0.5 0.4 0.3 0.2 VDD = 5V VREF = 10V SUPERIMPOSED: TA = -40C, +25C, +85C
5V
Preliminary Technical Data
VDD = 5V VREF = 10V TA = 25C
CLK (5V/DIV)
DNL (LSB)
0.1 0 -0.1 -0.2 -0.3 -0.4 0 512 1024 1536 2560 2048 CODE (Decimal) 3072 3584 4096
06492-012
VOUT (5V/DIV)
5V TIME (1s/DIV)
06492-015
-0.5
Figure 12. Linearity Error vs. Digital Code
4
Figure 15. Large Signal Settling Time
ALL BITS ON (MSB) B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 (LSB) B0 0 12 24 36 48 60 72 84 ALL BITS OFF
06492-013
VDD = 5V VREF = 10V TA = 25C
2
DATA BITS ON (ALL OTHER DATA BITS OFF)
0
-2
96
06492-016
-4 -2000
-1000 0 1000 OP AMP OFFSET VOS (V)
2000
100
1k
10k 100k FREQUENCY (Hz)
1M
108 10M
Figure 13. Linearity Error vs. External Op Amp Offset VOS
Figure 16. Reference Multiplying Bandwidth vs. Frequency and Code
VOUT (10mV/DIV)
VDD = 5V VREF = 10V fCLK = 2.5MHz CODE: 0x7FF TO 0x800
0.50
VDD = 5V TA = 25C
0.25
INL (LSB)
0
LD (5V/DIV)
-0.25
06492-014
20mV TIME (200ns/DIV)
-0.50 0 5 10
06492-017
|VREF | (V)
Figure 17. Linearity Error vs. Reference Voltage Figure 14. Midscale Transition Performance
Rev. PrA | Page 8 of 16
ATTENUATION (dB)
INL (LSB)
Preliminary Technical Data
1.2 SAMPLE SIZE = 50 -70 VREF = 4V p-p OUTPUT OP AMP: OP42 -75
AD5441
0.0320
NOMINAL CHANGE IN VOLTAGE (mV)
1.0
0.0180
0.8
CODE = 0xFFF
THD (dB)
0.6
-85 0.4 CODE = 0x000 0.2 -90
0.0056
0.0032
06492-018
0
100
200 300 400 HOURS OF OPERATION AT 150C
500
600
100
1k FREQUENCY (Hz)
10k
Figure 18. Long-Term Drift Accelerated by Burn-In
Figure 19. THD vs. Frequency
Rev. PrA | Page 9 of 16
06492-019
0
-95 10
0.0018 100k
THD (%)
-80
0.0100
AD5441 TERMINOLOGY
Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally expressed in LSBs or as a percentage of the full-scale reading. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of -1 LSB maximum over the operating temperature range ensures monotonicity. Gain Error Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For these DACs, ideal maximum output is VREF - 1 LSB. Gain error of the DACs is adjustable to zero with external resistance. Zero Scale Error Calculated from worst-case RREF: IZSE(LSB) = (RREF x ILKG x 4096)/VREF. Output Leakage Current Output leakage current is the current that flows into the DAC ladder switches when they are turned off. For the IOUT terminal, it can be measured by loading all 0s to the DAC and measuring the IOUT current. Output Capacitance Capacitance from IOUT1 to AGND. Digital-to-Analog Glitch Impulse The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-s or nV-s, depending on whether the glitch is measured as a current or voltage signal.
Preliminary Technical Data
Digital Feedthrough When the device is not selected, high frequency logic activity on the device's digital inputs may be capacitively coupled through the device and produce noise on the IOUT pins. This noise is coupled from the outputs of the device onto follow-on circuitry. This noise is digital feedthrough. Multiplying Feedthrough Error This is the error due to capacitive feedthrough from the DAC reference input to the DAC IOUT1 terminal when all 0s are loaded to the DAC. Total Harmonic Distortion (THD) The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower order harmonics, such as second to fifth, are included.
THD = 20 log V2 2 + V32 + V4 2 + V5 2 V1
Compliance Voltage Range The maximum range of (output) terminal voltage for which the device will provide the specified characteristics. Output Noise Spectral Density Calculation from en = 4KTRB where: K = Boltzmann Constant (J/K) R = Resistance () T = Resistor temperature (K) B = 1 Hz bandwidth
Rev. PrA | Page 10 of 16
Preliminary Technical Data PARAMETER DEFINITIONS
GENERAL CIRCUIT INFORMATION
The AD5441 is a 12-bit multiplying DAC with a low temperature coefficient. It contains an R-2R resistor ladder network, data input and control logic, and two data registers. The digital circuitry forms an interface in which serial data can be loaded under microprocessor control into a 12-bit shift register and then transferred, in parallel, to the 12-bit DAC register. The analog portion of the AD5441 contains an inverted R-2R ladder network consisting of silicon-chrome, highly stable (50 ppm/C), thin-film resistors, and 12 pairs of NMOS current-steering switches, see Figure 20. These switches steer binarily weighted currents into either IOUT or GND; this yields a constant current in each ladder leg, regardless of digital input code. This constant current results in a constant input resistance at VREF equal to R. The VREF input may be driven by any reference voltage or current, ac or dc that is within the limits stated in the Absolute Maximum Ratings.
VREF 10k 20k S1 10k 20k S2 10k 20k S3 20k S12 20k
*
AD5441
OUTPUT IMPEDANCE
The AD5441's output resistance, as in the case of the output capacitance, varies with the digital input code. This resistance, looking back into the IOUT terminal, may be between 10 k, the feedback resistor alone when all digital inputs are low, and 7.5 k, the feedback resistor in parallel with approximate 30 k of the R-2R ladder network resistance when any single bit logic is high. Static accuracy and dynamic performance will be affected by these variations.
APPLICATIONS INFORMATION
In most applications, linearity depends upon the potential of the IOUT and GND pins being at the same voltage potential. The DAC is connected to an external precision op amp inverting input. The external amplifiers noninverting input should be tied directly to ground without the usual bias current compensating resistor (see Figure 21 and Figure 22). The selected amplifier should have a low input bias current and low drift over temperature. The amplifiers input offset voltage should be nulled to less than 200 mV (less than 10% of 1 LSB). All grounded pins should tie to a single common ground point to avoid ground loops. The VDD power supply should have a low noise level with adequate bypassing. It is best to operate the AD5441 from the analog power supply and grounds.
GND 10k
*
IOUT RFEEDBACK
UNIPOLAR 2-QUADRANT MULTIPLYING
The most straightforward application of the AD5441 is in the 2-quadrant multiplying configuration shown in Figure 21. If the reference input signal is replaced with a fixed dc voltage reference, the DAC output will provide a proportional dc voltage output according to the transfer equation VOUT = -D/4096 x VREF where: D is the decimal data loaded into the DAC register. VREF is the externally applied reference voltage source.
VDD R2 RFB C1 IOUT1 GND
BIT 1 (MSB)
BIT 2 BIT 3 DIGITAL INPUTS
BIT 12 (LSB)
*THESE SWITCHES PERMANENTLY ON. NOTES 1. SWITCHES SHOWN FOR DIGITAL INPUTS HIGH.
06492-021
Figure 20. Simplified DAC Circuit
The 12 output current steering NMOS FET switches are in series with each R-2R resistor. To further ensure accuracy across the full temperature range, permanently on MOS switches were included in series with the feedback resistor and the R-2R ladder's terminating resistor. Figure 20 shows the location of the series switches. During any testing of the resistor ladder or RFEEDBACK (such as incoming inspection), VDD must be present to turn on these series switches.
VDD VREF VREF LD
R1
AD5441
CLK SRI
A1 VOUT = 0 TO -VREF AGND
CONTROLLER
04587-009
NOTES 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. 2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 21. Unipolar (2-Quadrant) Operation
Rev. PrA | Page 11 of 16
AD5441
BIPOLAR 4-QUADRANT MULTIPLYING
Figure 22 shows a suggested circuit to achieve 4-quadrant multiplying operation. The summing amplifier multiplies VOUT1 by 2 and offsets the output with the reference voltage so that a midscale digital input code of 2048 places VOUT2 at 0 V. The negative full-scale voltage will be VREF when the DAC is loaded with all zeros. The positive full-scale output will be -(VREF - 1 LSB) when the DAC is loaded with all ones. Therefore, the digital coding is offset binary. The voltage output transfer equation for various input data and reference (or signal) values follows VOUT2 = (D/2048 - 1) - VREF where: D is the decimal data loaded into the DAC register. VREF is the externally applied reference voltage source.
R3 20k VDD R2 RFB C1 IOUT1 GND R4 10k A2 VOUT = -VREF TO +VREF R5 20k
Preliminary Technical Data
INTERFACE LOGIC INFORMATION
The AD5441 has been designed for ease of operation. The timing diagram in Figure 5 illustrates the input register loading sequence. Note that the most significant bit (MSB) is loaded first. Once the 12-bit input register is full, the data is transferred to the DAC register by taking LD momentarily low.
DIGITAL SECTION
The AD5441's digital inputs, SRI, LD, and CLK, are TTL compatible. The input voltage levels affect the amount of current drawn from the supply; peak supply current occurs as the digital input (VIN) passes through the transition region. See Figure 8 for the supply current vs. logic input voltage graph. Maintaining the digital input voltage levels as close as possible to the supplies, VDD and GND, minimizes supply current consumption. The AD5441's digital inputs have been designed with ESD resistance incorporated through careful layout and the inclusion of input protection circuitry. Figure 23 shows the input protection diodes and series resistor; this input structure is duplicated on each digital input. High voltage static charges applied to the inputs are shunted to the supply and ground rails through forward-biased diodes. These protection diodes were designed to clamp the inputs to well below dangerous levels during static discharge conditions.
VDD
VDD VREF 10V VREF LD
R1
AD5441
CLK SRI
A1
AGND CONTROLLER NOTES 1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC. 2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4. 3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A2 IS A HIGH SPEED AMPLIFIER.
04587-010
LD, CLK, SRI
5k
Figure 22. Bipolar (4-Quadrant) Operation
GND
06492-020
Figure 23. Digital Input Protection
Rev. PrA | Page 12 of 16
Preliminary Technical Data OUTLINE DIMENSIONS
3.25 3.00 2.75 0.55 0.40 0.30 2.25 2.00 1.75
5
AD5441
1.89 1.74 1.59
0.25 0.20 0.15
8
1.95 1.75 1.55 PIN 1 INDICATOR
TOP VIEW
0.60 0.45 0.30
EXPOSEDPAD 4
BOTTOM VIEW
1
0.15 0.10 0.05
2.95 2.75 2.55 12 MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF
0.50 BSC
1.00 0.85 0.80
Figure 24. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] (CP-8-1) Dimensions are shown in millimeters
3.20 3.00 2.80
3.20 3.00 2.80 PIN 1
8
5
1
5.15 4.90 4.65
4
0.65 BSC 0.95 0.85 0.75 0.15 0.00 0.38 0.22 SEATING PLANE 1.10 MAX 8 0 0.80 0.60 0.40
0.23 0.08
COPLANARITY 0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 25. 8-Lead Mini Small Outline Package [MINI_SO] (RM-8) Dimensions are shown in millimeters
Rev. PrA | Page 13 of 16
031207-A
SEATING PLANE
AD5441 NOTES
Preliminary Technical Data
Rev. PrA | Page 14 of 16
Preliminary Technical Data NOTES
AD5441
Rev. PrA | Page 15 of 16
AD5441 NOTES
Preliminary Technical Data
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06492-0-3/07(PrA)
Rev. PrA | Page 16 of 16

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